There are three different types of clocking architectures supported by PCIe:

Common Refclk is the most widely supported architecture among commercially available devices. However, the same clock source must be distributed to every PCIe device while keeping the clock-to-clock skew to less than 12 ns between devices. This can be a problem with large circuit boards or when crossing a backplane connector to another circuit board.

If a low-skew configuration isn’t workable, such as in a long cable implementation, the Separate Refclk architecture, with independent clocks at each end, can be used. But Gen 2.0 base specification did not allow the SSC on the Separate Refclk implementation. It was only enabled through ECN: Separate Refclk Independent SSC (SRIS) Architecture in 2013 which became part of the 3.1 base specifications released in Nov 2013.

The Data Clocked Refclk architecture is the simplest, as it requires only one clock source, at the transmitter. The receiver extracts and syncs to the clock embedded in the transmitted data. Data-clocked architecture was introduced when the PCIe 2.0 standard was released in 2007.

You can learn more about clocking architectures here.

To learn more about SRIS, here is yet another insightful short video from Synopsys Fellow John Stonick.